This invention relates to a system semiconductor device and a method of manufacturing the same, and in particular, to a system semiconductor device having a plurality of functional blocks.
The conventional system LSI (Large-Scale-Integrated circuit) generally includes a plurality of functional blocks. Herein, it is to be noted that the functional block serves as a circuit unit for realizing a specific function. In such a system LSI, complex functions are integrated on one chip.
The conventional method of manufacturing the system LSI has been carried out as follows.
A plurality of functional blocks are first fabricated on a silicon chip. Thereafter, a circuit wiring layer which electrically connects the functional blocks to each other is formed on the silicon chip by the use of a metal vaporizing method or a metal plating method.
Subsequently, an insulating film is formed thereon and the circuit wiring layer and the insulating layer are sequentially laminated. Thereby, a global wiring layer serving as a multi-wiring layer is formed on the silicon chip.
Thus, a plurality of circuit wiring layers and insulating layers conventionally has been laminated for many times to manufacture the system LSI.
However, the conventional system LSI has the following problems.
First, manufacturing yield is degraded. This reason will be explained below. Namely, an external stress is applied or stress-migration occurs because a plurality of circuit wiring layers and insulating layers are laminated.
Under this circumstance, the circuit wiring layer is peeled from the insulating layer. Consequently, a physical strength is inevitably lowered.
Further, an electrical connection between layers is damaged. In consequence, electrical connection reliability is readily degraded.
Second, a manufacturing duration becomes long. This reason will be explained as follows.
Namely, after the system LSI is fabricated, a plurality circuit wiring layers and insulating layers are alternately laminated on a system LSI cell. To this end, complex and many steps are inevitably required.
Third, selection degree of freedom concerning materials of the global wiring layer and manufacturing processes is lowered. This reason will be described below.
That is, the manufacturing process of the global wiring layer or the materials of the circuit wiring layers and the insulating layers are restricted in dependency upon a laminating process. Consequently, the manufacturing process and the material can not freely or suitably selected.
Fourth, physical characteristics and electrical characteristics are degraded, and the manufacturing cost becomes high. This reason will be explained as follows.
The manufacturing process of the global wiring line layer or the materials of the circuit wiring layers and the insulating layers are restricted in accordance with the laminating process. Consequently, the manufacturing process and the material can not freely or suitably selected.
Fifth, the electrical characteristic for a high-frequency signal is degraded. This reason will be explained below.
That is, a system LSI cell portion and the global wiring line layer are adjacently arranged to each other. In consequence, dielectric constants are enhanced to each other, and impedance of the circuit is also increased.